Vulkan.Core10.Enums.AccessFlagBits · vulkan-3.27

typetype AccessFlags = AccessFlagBits

newtypenewtype AccessFlagBits

VkAccessFlagBits - Bitmask specifying memory access types that will participate in a memory dependency

Description

These values all have the same meaning as the equivalently named values for AccessFlags2.

ACCESS_NONE specifies no accesses.
ACCESS_MEMORY_READ_BIT specifies all read accesses. It is always valid in any access mask, and is treated as equivalent to setting all READ access flags that are valid where it is used.
ACCESS_MEMORY_WRITE_BIT specifies all write accesses. It is always valid in any access mask, and is treated as equivalent to setting all WRITE access flags that are valid where it is used.
ACCESS_INDIRECT_COMMAND_READ_BIT specifies read access to indirect command data read as part of an indirect build, trace, drawing or dispatching command. Such access occurs in the PIPELINE_STAGE_DRAW_INDIRECT_BIT pipeline stage.
ACCESS_INDEX_READ_BIT specifies read access to an index buffer as part of an indexed drawing command, bound by cmdBindIndexBuffer2 and cmdBindIndexBuffer. Such access occurs in the PIPELINE_STAGE_VERTEX_INPUT_BIT pipeline stage.
ACCESS_VERTEX_ATTRIBUTE_READ_BIT specifies read access to a vertex buffer as part of a drawing command, bound by cmdBindVertexBuffers. Such access occurs in the PIPELINE_STAGE_VERTEX_INPUT_BIT pipeline stage.
ACCESS_UNIFORM_READ_BIT specifies read access to a uniform buffer in any shader pipeline stage.
ACCESS_INPUT_ATTACHMENT_READ_BIT specifies read access to an input attachment within a render pass during subpass shading or fragment shading. Such access occurs in the PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI or PIPELINE_STAGE_FRAGMENT_SHADER_BIT pipeline stage.
ACCESS_SHADER_READ_BIT specifies read access to a uniform texel buffer, sampled image, storage buffer, physical storage buffer, shader binding table, storage tensor, storage texel buffer, or storage image in any shader pipeline stage.
ACCESS_SHADER_WRITE_BIT specifies write access to a storage buffer, physical storage buffer, storage tensor, storage texel buffer, or storage image in any shader pipeline stage.
ACCESS_COLOR_ATTACHMENT_READ_BIT specifies read access to a color attachment, such as via blending (other than advanced blend operations), logic operations or certain render pass load operations in the PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage or via fragment shader tile image reads in the PIPELINE_STAGE_FRAGMENT_SHADER_BIT pipeline stage.
ACCESS_COLOR_ATTACHMENT_WRITE_BIT specifies write access to a color attachment during a render pass or via certain render pass load, store, and multisample resolve operations. This includes multisample resolve operations for depth/stencil resolve attachments. Such access occurs in the PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage.
ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT specifies read access to a depth/stencil attachment, via depth or stencil operations or certain render pass load operations in the PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT or PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT pipeline stages or via fragment shader tile image reads in the PIPELINE_STAGE_FRAGMENT_SHADER_BIT pipeline stage.
ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT specifies write access to a depth/stencil attachment, via depth or stencil operations or certain render pass load and store operations. Such access occurs in the PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT or PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT pipeline stages.
ACCESS_TRANSFER_READ_BIT specifies read access to an image, tensor, or buffer in a copy operation. Such access occurs in the PIPELINE_STAGE_2_ALL_TRANSFER_BIT pipeline stage.
ACCESS_TRANSFER_WRITE_BIT specifies write access to an image, tensor, or buffer in a clear or copy operation. Such access occurs in the PIPELINE_STAGE_2_ALL_TRANSFER_BIT pipeline stage.
ACCESS_HOST_READ_BIT specifies read access by a host operation. Accesses of this type are not performed through a resource, but directly on memory. Such access occurs in the PIPELINE_STAGE_HOST_BIT pipeline stage.
ACCESS_HOST_WRITE_BIT specifies write access by a host operation. Accesses of this type are not performed through a resource, but directly on memory. Such access occurs in the PIPELINE_STAGE_HOST_BIT pipeline stage.
ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT specifies read access to a predicate as part of conditional rendering. Such access occurs in the PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT pipeline stage.
ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT specifies write access to a transform feedback buffer made when transform feedback is active. Such access occurs in the PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT pipeline stage.
ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT specifies read access to a transform feedback counter buffer which is read when cmdBeginTransformFeedbackEXT executes. Such access occurs in the PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT pipeline stage.
ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT specifies write access to a transform feedback counter buffer which is written when cmdEndTransformFeedbackEXT executes. Such access occurs in the PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT pipeline stage.
ACCESS_COMMAND_PREPROCESS_READ_BIT_NV specifies reads from buffer inputs to cmdPreprocessGeneratedCommandsNV. Such access occurs in the PIPELINE_STAGE_COMMAND_PREPROCESS_BIT_NV pipeline stage.
ACCESS_COMMAND_PREPROCESS_WRITE_BIT_NV specifies writes to the target command buffer preprocess outputs in cmdPreprocessGeneratedCommandsNV. Such access occurs in the PIPELINE_STAGE_COMMAND_PREPROCESS_BIT_NV pipeline stage.
ACCESS_COMMAND_PREPROCESS_READ_BIT_EXT specifies reads from buffer inputs to cmdPreprocessGeneratedCommandsEXT. Such access occurs in the PIPELINE_STAGE_COMMAND_PREPROCESS_BIT_EXT pipeline stage.
ACCESS_COMMAND_PREPROCESS_WRITE_BIT_EXT specifies writes to the target command buffer preprocess outputs in cmdPreprocessGeneratedCommandsEXT. Such access occurs in the PIPELINE_STAGE_COMMAND_PREPROCESS_BIT_EXT pipeline stage.
ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT specifies read access to color attachments, including advanced blend operations. Such access occurs in the PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage.
ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI specifies read access to an invocation mask image in the PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI pipeline stage.
ACCESS_ACCELERATION_STRUCTURE_READ_BIT_KHR specifies read access to an acceleration structure as part of a trace, build, or copy command, or to an acceleration structure scratch buffer as part of a build command. Such access occurs in the PIPELINE_STAGE_RAY_TRACING_SHADER_BIT_KHR pipeline stage or PIPELINE_STAGE_ACCELERATION_STRUCTURE_BUILD_BIT_KHR pipeline stage.
ACCESS_ACCELERATION_STRUCTURE_WRITE_BIT_KHR specifies write access to an acceleration structure or acceleration structure scratch buffer as part of a build or copy command. Such access occurs in the PIPELINE_STAGE_ACCELERATION_STRUCTURE_BUILD_BIT_KHR pipeline stage.
ACCESS_FRAGMENT_DENSITY_MAP_READ_BIT_EXT specifies read access to a fragment density map attachment during dynamic fragment density map operations Such access occurs in the PIPELINE_STAGE_FRAGMENT_DENSITY_PROCESS_BIT_EXT pipeline stage.
ACCESS_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR specifies read access to a fragment shading rate attachment during rasterization. Such access occurs in the PIPELINE_STAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR pipeline stage.
ACCESS_SHADING_RATE_IMAGE_READ_BIT_NV specifies read access to a shading rate image during rasterization. Such access occurs in the PIPELINE_STAGE_SHADING_RATE_IMAGE_BIT_NV pipeline stage. It is equivalent to PIPELINE_STAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR.

Certain access types are only performed by a subset of pipeline stages. Any synchronization command that takes both stage masks and access masks uses both to define the access scopes - only the specified access types performed by the specified stages are included in the access scope. An application must not specify an access flag in a synchronization command if it does not include a pipeline stage in the corresponding stage mask that is able to perform accesses of that type. The following table lists, for each access flag, which pipeline stages can perform that type of access.

Description

See Also

Constructors