Vulkan.Core13.Enums.AccessFlags2

VkAccessFlagBits2 - Access flags for VkAccessFlags2

Description

• ACCESS_2_NONE specifies no accesses.

• ACCESS_2_MEMORY_READ_BIT specifies all read accesses. It is always valid in any access mask, and is treated as equivalent to setting all READ access flags that are valid where it is used.

• ACCESS_2_MEMORY_WRITE_BIT specifies all write accesses. It is always valid in any access mask, and is treated as equivalent to setting all WRITE access flags that are valid where it is used.

• ACCESS_2_INDIRECT_COMMAND_READ_BIT specifies read access to command data read from indirect buffers as part of an indirect build, trace, drawing or dispatch command. Such access occurs in the PIPELINE_STAGE_2_DRAW_INDIRECT_BIT pipeline stage. It also specifies read access to command data read from indirect buffers as part of a copy command with access occurring in the PIPELINE_STAGE_2_COPY_INDIRECT_BIT_KHR pipeline stage.

• ACCESS_2_INDEX_READ_BIT specifies read access to an index buffer as part of an indexed drawing command, bound by cmdBindIndexBuffer2 and cmdBindIndexBuffer. Such access occurs in the PIPELINE_STAGE_2_INDEX_INPUT_BIT pipeline stage.

• ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT specifies read access to a vertex buffer as part of a drawing command, bound by cmdBindVertexBuffers. Such access occurs in the PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT pipeline stage.

• ACCESS_2_UNIFORM_READ_BIT specifies read access to a uniform buffer in any shader pipeline stage.

• ACCESS_2_INPUT_ATTACHMENT_READ_BIT specifies read access to an input attachment within a render pass during subpass shading or fragment shading. Such access occurs in the PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI or PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT pipeline stage.

• ACCESS_2_SHADER_SAMPLED_READ_BIT specifies read access to a uniform texel buffer or sampled image in any shader pipeline stage.

• ACCESS_2_SHADER_STORAGE_READ_BIT specifies read access to a storage buffer, physical storage buffer, storage texel buffer, or storage image in any shader pipeline stage.

• ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR specifies read access to a shader binding table in any shader pipeline stage.

• ACCESS_2_SHADER_READ_BIT is equivalent to the logical OR of:

  • ACCESS_2_SHADER_SAMPLED_READ_BIT

  • ACCESS_2_SHADER_STORAGE_READ_BIT

  • ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR

  • ACCESS_2_SHADER_TILE_ATTACHMENT_READ_BIT_QCOM

• ACCESS_2_SHADER_STORAGE_WRITE_BIT specifies write access to a storage buffer, physical storage buffer, storage texel buffer, or storage image in any shader pipeline stage.

• ACCESS_2_SHADER_WRITE_BIT is equivalent to ACCESS_2_SHADER_STORAGE_WRITE_BIT.

• ACCESS_2_COLOR_ATTACHMENT_READ_BIT specifies read access to a color attachment, such as via blending (other than advanced blend operations), logic operations or certain render pass load operations in the PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage or via fragment shader tile image reads in the PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT pipeline stage.

• ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT specifies write access to a color attachment during a render pass or via certain render pass load, store, and multisample resolve operations. This includes multisample resolve operations for depth/stencil resolve attachments. Such access occurs in the PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage.

• ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT specifies read access to a depth/stencil attachment, via depth or stencil operations or certain render pass load operations in the PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT or PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT pipeline stages or via fragment shader tile image reads in the PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT pipeline stage.

• ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT specifies write access to a depth/stencil attachment, via depth or stencil operations or certain render pass load and store operations. Such access occurs in the PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT or PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT pipeline stages.

• ACCESS_2_TRANSFER_READ_BIT specifies read access to an image or buffer in a copy operation. Such access occurs in the PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, or PIPELINE_STAGE_2_RESOLVE_BIT pipeline stages.

• ACCESS_2_TRANSFER_WRITE_BIT specifies write access to an image or buffer in a clear or copy operation. Such access occurs in the PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_CLEAR_BIT, or PIPELINE_STAGE_2_RESOLVE_BIT pipeline stages.

• ACCESS_2_HOST_READ_BIT specifies read access by a host operation. Accesses of this type are not performed through a resource, but directly on memory. Such access occurs in the PIPELINE_STAGE_2_HOST_BIT pipeline stage.

• ACCESS_2_HOST_WRITE_BIT specifies write access by a host operation. Accesses of this type are not performed through a resource, but directly on memory. Such access occurs in the PIPELINE_STAGE_2_HOST_BIT pipeline stage.

• ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT specifies read access to a predicate as part of conditional rendering. Such access occurs in the PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT pipeline stage.

• ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT specifies write access to a transform feedback buffer made when transform feedback is active. Such access occurs in the PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT pipeline stage.

• ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT specifies read access to a transform feedback counter buffer which is read when cmdBeginTransformFeedbackEXT executes. Such access occurs in the PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT pipeline stage.

• ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT specifies write access to a transform feedback counter buffer which is written when cmdEndTransformFeedbackEXT executes. Such access occurs in the PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT pipeline stage.

• ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV specifies reads from buffer inputs to cmdPreprocessGeneratedCommandsNV. Such access occurs in the PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV pipeline stage.

• ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV specifies writes to the target command buffer preprocess outputs. Such access occurs in the PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV pipeline stage.

• ACCESS_2_COMMAND_PREPROCESS_READ_BIT_EXT specifies reads from buffer inputs to cmdPreprocessGeneratedCommandsEXT. Such access occurs in the PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_EXT pipeline stage.

• ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_EXT specifies writes to the target command buffer preprocess outputs. Such access occurs in the PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_EXT pipeline stage.

• ACCESS_2_MEMORY_DECOMPRESSION_READ_BIT_EXT specifies read access to memory in decompression commands cmdDecompressMemoryEXT and cmdDecompressMemoryIndirectCountEXT. Such access occurs in PIPELINE_STAGE_2_MEMORY_DECOMPRESSION_BIT_EXT pipeline stage.

• ACCESS_2_MEMORY_DECOMPRESSION_WRITE_BIT_EXT specifies write access to memory in decompression commands cmdDecompressMemoryEXT and cmdDecompressMemoryIndirectCountEXT. Such access occurs in PIPELINE_STAGE_2_MEMORY_DECOMPRESSION_BIT_EXT pipeline stage.

• ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT specifies read access to color attachments, including advanced blend operations. Such access occurs in the PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage.

• ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI specifies read access to an invocation mask image in the PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI pipeline stage.

• ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR specifies read access to an acceleration structure as part of a trace, build, or copy command, or to an acceleration structure scratch buffer as part of a build command. Such access occurs in the PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR pipeline stage or PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR pipeline stage.

• ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR specifies write access to an acceleration structure or acceleration structure scratch buffer as part of a build or copy command. Such access occurs in the PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR pipeline stage.

• ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT specifies read access to a fragment density map attachment during dynamic fragment density map operations. Such access occurs in the PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT pipeline stage.

• ACCESS_2_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR specifies read access to a fragment shading rate attachment during rasterization. Such access occurs in the PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR pipeline stage.

• ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV specifies read access to a shading rate image during rasterization. Such access occurs in the PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV pipeline stage. It is equivalent to ACCESS_2_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR.

• VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHR specifies read access to an image or buffer resource in a video decode operation. Such access occurs in the VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR pipeline stage.

• VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR specifies write access to an image or buffer resource in a video decode operation. Such access occurs in the VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR pipeline stage.

• VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR specifies read access to an image or buffer resource in a video encode operation. Such access occurs in the VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR pipeline stage.

• VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR specifies write access to an image or buffer resource in a video encode operation. Such access occurs in the VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR pipeline stage.

• ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT specifies read access to a descriptor buffer in any shader pipeline stage.

• ACCESS_2_OPTICAL_FLOW_READ_BIT_NV specifies read access to an image or buffer resource as part of a optical flow operation. Such access occurs in the PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV pipeline stage.

• ACCESS_2_OPTICAL_FLOW_WRITE_BIT_NV specifies write access to an image or buffer resource as part of a optical flow operation. Such access occurs in the PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV pipeline stage.

• ACCESS_2_MICROMAP_WRITE_BIT_EXT specifies write access to a micromap object. Such access occurs in the PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT pipeline stage.

• ACCESS_2_MICROMAP_READ_BIT_EXT specifies read access to a micromap object. Such access occurs in the PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT and PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR pipeline stages.

• ACCESS_2_SHADER_TILE_ATTACHMENT_READ_BIT_QCOM specifies read access to a tile attachment. Such access occurs in the PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT or PIPELINE_STAGE_2_COMPUTE_SHADER_BIT pipeline stages.

• ACCESS_2_SHADER_TILE_ATTACHMENT_WRITE_BIT_QCOM specifies write access to a tile attachment. Such access occurs in the PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT or PIPELINE_STAGE_2_COMPUTE_SHADER_BIT pipeline stages.

• ACCESS_2_DATA_GRAPH_READ_BIT_ARM specifies read access to resources in the PIPELINE_STAGE_2_DATA_GRAPH_BIT_ARM pipeline stage.

• ACCESS_2_DATA_GRAPH_WRITE_BIT_ARM specifies write access to resources in the PIPELINE_STAGE_2_DATA_GRAPH_BIT_ARM pipeline stage.

• ACCESS_2_SAMPLER_HEAP_READ_BIT_EXT specifies read access to a sampler heap in any shader pipeline stage.

• ACCESS_2_RESOURCE_HEAP_READ_BIT_EXT specifies read access to a resource heap in any shader pipeline stage.

Certain access types are only performed by a subset of pipeline stages, as described in more detail for AccessFlagBits. The Supported Access Types table lists, for each access flag, which pipeline stages can perform that type of access.

In situations where an application wishes to select all access types for a given set of pipeline stages, ACCESS_2_MEMORY_READ_BIT or ACCESS_2_MEMORY_WRITE_BIT can be used. This is particularly useful when specifying stages that only have a single access type.

The AccessFlags2 bitmask goes beyond the 31 individual bit flags allowable within a C99 enum, which is how AccessFlagBits is defined. The first 31 values are common to both, and are interchangeable.

See Also

VK_KHR_synchronization2, VK_VERSION_1_3, AccessFlags2