First integer register number. zero register.
Moduleghc-9.14.1GHC2021
GHC.CmmToAsm.RV64.Regs
Contents
Synopsis
- value x0RegNo
- value x1RegNo
- value raRegNo
- value x5RegNo
- value t0RegNo
- value x7RegNo
- value t2RegNo
- value x28RegNo
- value t3RegNo
- value x31RegNo
- value t6RegNo
- value tmpRegNo
- value d0RegNo
- value ft0RegNo
- value d7RegNo
- value ft7RegNo
- value d31RegNo
- value x10RegNo
- value a0RegNo
- value x17RegNo
- value a7RegNo
- value d10RegNo
- value fa0RegNo
- value d17RegNo
- value fa7RegNo
- value zeroReg
- value raReg
- value spMachReg
- value tmpReg
- value allMachRegNos
- value allocatableRegs
- value allGpArgRegs
- value allFpArgRegs
- data AddrMode
- data Imm
- value litToImm
- value virtualRegSqueeze
- value realRegSqueeze
- value mkVirtualReg
- value classOfRealReg
- value regDotColor
- Packageghc-9.14.1
- Exports41
- LanguageGHC2021
- LicenceBSD-3-Clause
- SourceRegs.hs
Registers
return address register
return address register
Last integer register number. Used as TMP (IP) register.
Last integer register number. Used as TMP (IP) register.
Last integer register number. Used as TMP (IP) register.
First floating point register.
First floating point register.
Last floating point register.
All machine register numbers.
Registers available to the register allocator.
These are all registers minus those with a fixed role in RISCV ABI (zero, lr, sp, gp, tp, fp, tmp) and GHC RTS (Base, Sp, Hp, HpLim, R1..R8, F1..F6, D1..D6.)
Integer argument registers according to the calling convention
Floating point argument registers according to the calling convention
Addressing modes
Addressing modes
Constructors
AddrRegImm Reg ImmA register plus some immediate integer, e.g.
8(sp)or-16(sp). The offset needs to fit into 12bits.AddrReg RegA register
Immediates
regSqueeze_class reg Calculate the maximum number of register colors that could be denied to a node of this class due to having this reg as a neighbour.