Constructors
COMMENT FastStringLOCATION Int Int Int StringLDATA Section (Alignment, RawCmmStatics)NEWBLOCK BlockIdUNWIND CLabel UnwindTableDELTA IntMOV Format Operand OperandX86 scalar move instruction.
The format is the format the destination is written to. For an XMM register, using a scalar format means that we don't care about the upper bits, while using a vector format means that we care about the upper bits, even though we are only writing to the lower bits.
See also Note [Allocated register formats] in GHC.CmmToAsm.Reg.Linear.
MOVD Format Format Operand OperandMOVD/MOVQ SSE2 instructions (bitcast between a general purpose register and a float register).
CMOV Cond Format Operand RegMOVZxL Format Operand OperandThe format argument is the size of operand 1 (the number of bits we keep) We always zero *all* high bits, even though this isn't how the actual instruction works. The code generator also seems to rely on this behaviour and it's faster to execute on many cpus as well so for now I'm just documenting the fact.
MOVSxL Format Operand OperandLEA Format Operand OperandADD Format Operand OperandADC Format Operand OperandSUB Format Operand OperandSBB Format Operand OperandMUL Format Operand OperandMUL2 Format OperandIMUL Format Operand OperandIMUL2 Format OperandDIV Format OperandIDIV Format OperandADD_CC Format Operand OperandSUB_CC Format Operand OperandAND Format Operand OperandOR Format Operand OperandXOR Format Operand OperandNOT Format OperandNEGI Format OperandBSWAP Format RegVAND Format Operand Reg RegVOR Format Operand Reg RegVXOR Format Operand Reg RegSHL Format Operand OperandSAR Format Operand OperandSHR Format Operand OperandSHRD Format Operand Operand OperandSHLD Format Operand Operand OperandBT Format Imm OperandNOPX87Store Format AddrModeCVTSS2SD Reg RegCVTSD2SS Reg RegCVTTSS2SIQ Format Operand RegCVTTSD2SIQ Format Operand RegCVTSI2SS Format Operand RegCVTSI2SD Format Operand RegFMA3 Format FMASign FMAPermutation Operand Reg RegFMA3 fused multiply-add operations.
FDIV Format Operand RegSQRT Format Operand RegTEST Format Operand OperandCMP Format Operand OperandSETCC Cond OperandPUSH Format OperandPOP Format OperandJMP Operand [RegWithFormat]JXX Cond BlockIdJXX_GBL Cond ImmJMP_TBL Operand [Maybe JumpDest] Section CLabel !(Maybe CLabel)CALL (Either Imm Reg) [RegWithFormat]X86 call instruction
CLTD FormatFETCHGOT RegFETCHPC RegPOPCNT Format Operand RegLZCNT Format Operand RegTZCNT Format Operand RegBSF Format Operand RegBSR Format Operand RegPDEP Format Operand Operand RegPEXT Format Operand Operand RegPREFETCH PrefetchVariant Format OperandLOCK InstrXADD Format Operand OperandCMPXCHG Format Operand OperandXCHG Format Operand RegMFENCEVBROADCAST Format Operand RegVPBROADCAST Format Format Operand RegVEXTRACT Format Imm Reg OperandINSERTPS Format Imm Operand RegVINSERTPS Format Imm Operand Reg RegPINSR Format Format Imm Operand RegPEXTR Format Format Imm Reg OperandMOVU Format Operand OperandSSE2 unaligned move of floating-point vectors
VMOVU Format Operand OperandAVX unaligned move of floating-point vectors
MOVL Format Operand OperandSSE2 move between memory and low-part of an xmm register
MOVH Format Operand OperandSSE move between memory and high-part of an xmm register
MOVDQU Format Operand OperandSSE2 unaligned move of integer vectors
VMOVDQU Format Operand OperandAVX unaligned move of integer vectors
VMOV_MERGE Format Reg Reg RegAlias for VMOVSS/VMOVSD, used to merge two vectors
PXOR Format Operand RegVPXOR Format Operand Reg RegPAND Format Operand RegPANDN Format Operand RegVPAND Format Operand Reg RegPOR Format Operand RegVPOR Format Operand Reg RegVADD Format Operand Reg RegVSUB Format Operand Reg RegVMUL Format Operand Reg RegVDIV Format Operand Reg RegPADD Format Operand RegPSUB Format Operand RegPMULL Format Operand RegVPMULL Format Operand Reg RegPMULUDQ Format Operand RegPABS Format Operand RegVPABS Format Operand RegVSQRT Format Operand RegPCMPGT Format Operand RegSHUF Format Imm Operand RegVSHUF Format Imm Operand Reg RegPSHUFB Format Operand RegPSHUFLW Format Imm Operand RegPSHUFHW Format Imm Operand RegPSHUFD Format Imm Operand RegVPSHUFD Format Imm Operand RegBLEND Format Imm Operand RegVBLEND Format Imm Operand Reg RegPBLENDW Format Imm Operand RegMOVHLPS Format Reg RegMove two 32-bit floats from the high part of an xmm register to the low part of another xmm register.
If the format is a vector format, the destination register is treated as the second source. If the format is FF32 or FF64, the destination register is not treated as a source.
VMOVHLPS Format Reg Reg RegMOVLHPS Format Reg RegVMOVLHPS Format Reg Reg RegUNPCKL Format Operand RegVUNPCKL Format Operand Reg RegUNPCKH Format Operand RegVUNPCKH Format Operand Reg RegPUNPCKLQDQ Format Operand RegPUNPCKLDQ Format Operand RegPUNPCKLWD Format Operand RegPUNPCKLBW Format Operand RegPUNPCKHQDQ Format Operand RegPUNPCKHDQ Format Operand RegPUNPCKHWD Format Operand RegPUNPCKHBW Format Operand RegPACKUSWB Format Operand RegPSLL Format Operand RegPSLLDQ Format Imm RegPSRA Format Operand RegPSRL Format Operand RegPSRLDQ Format Imm RegPALIGNR Format Imm Operand RegMINMAX MinOrMax MinMaxType Format Operand RegVMINMAX MinOrMax MinMaxType Format Operand Reg Reg
Instances1Instruction
Instruction InstrDefined in ghc-10.0.0.20260917 · GHC.CmmToAsm.X86 · orphanInstruction instance for x86 instruction set.