Used to store the register assignment on entry to a basic block. We use this to handle join points, where multiple branch instructions target a particular label. We have to insert fixup code to make the register assignments from the different sources match up.
Moduleghc-10.0.0.20260917GHC2024
GHC.CmmToAsm.Reg.Linear.Base
Put common type definitions here to break recursive module dependencies.
Synopsis
- data BlockAssignment
- value lookupBlockAssignment
- value lookupFirstUsed
- value emptyBlockAssignment
- value updateBlockAssignment
- data VLoc
- data Loc
- newtype IgnoreFormat
- value regsOfLoc
- data RealRegUsage
- data SpillReason
- data RegAllocStats
- data RA_State
- Packageghc-10.0.0.20260917
- Exports13
- LanguageGHC2024
- LicenceBSD-3-Clause
- SourceBase.hs
Find the register mapping for a specific BlockId.
Lookup which register a virtual register was first assigned to.
An initial empty BlockAssignment
Add new register mappings for a specific block.
Where a vreg is currently stored.
A temporary can be marked as living in both a register and memory (InBoth), for example if it was recently loaded from a spill location. This makes it cheap to spill (no save instruction required), but we have to be careful to turn this into InReg if the value in the register is changed.
Instances4Eq, Ord, Show, Outputable
Where a virtual register is stored, together with the format it is stored at.
See VLoc.
Constructors
Instances3Outputable, Eq, Ord
Outputable LocDefined in ghc-10.0.0.20260917 · GHC.CmmToAsm.Reg.Linear.BaseEq (IgnoreFormat Loc)Defined in ghc-10.0.0.20260917 · GHC.CmmToAsm.Reg.Linear.BaseOrd (IgnoreFormat Loc)Defined in ghc-10.0.0.20260917 · GHC.CmmToAsm.Reg.Linear.Base
A newtype used to hang off Eq and Ord instances for Loc which
ignore the format, as used in GHC.CmmToAsm.Reg.Linear.JoinToTargets.
Constructors
Instances2Eq, Ord
Eq (IgnoreFormat Loc)Defined in ghc-10.0.0.20260917 · GHC.CmmToAsm.Reg.Linear.BaseOrd (IgnoreFormat Loc)Defined in ghc-10.0.0.20260917 · GHC.CmmToAsm.Reg.Linear.Base
Get the reg numbers stored in this Loc.
Constructors
Instances2Show, Outputable
Show RealRegUsageDefined in ghc-10.0.0.20260917 · GHC.CmmToAsm.Reg.Linear.BaseOutputable RealRegUsageDefined in ghc-10.0.0.20260917 · GHC.CmmToAsm.Reg.Linear.Base
Reasons why instructions might be inserted by the spiller. Used when generating stats for -ddrop-asm-stats.
Constructors
SpillAlloc !Uniquevreg was spilled to a slot so we could use its current hreg for another vreg
SpillClobber !Uniquevreg was moved because its hreg was clobbered
SpillLoad !Uniquevreg was loaded from a spill slot
SpillJoinRR !Uniquereg-reg move inserted during join to targets
SpillJoinRM !Uniquereg-mem move inserted during join to targets
Used to carry interesting stats out of the register allocator.
Constructors
RegAllocStatsra_spillInstrs :: UniqFM Unique [Int]ra_fixupList :: [(BlockId, BlockId, BlockId)](from,fixup,to) : We inserted fixup code between from and to
The register allocator state
Constructors
RA_Statera_blockassig :: BlockAssignment freeRegsthe current mapping from basic blocks to the register assignments at the beginning of that block.
ra_freeregs :: !freeRegsfree machine registers
ra_assig :: RegMap Locassignment of temps to locations
ra_delta :: Intcurrent stack delta
ra_stack :: StackMapfree stack slots for spilling
ra_us :: DUniqSupplyunique supply for generating names for join point fixup blocks.
ra_spills :: [SpillReason]Record why things were spilled, for -ddrop-asm-stats. Just keep a list here instead of a map of regs -> reasons. We don't want to slow down the allocator if we're not going to emit the stats.
ra_config :: !NCGConfigNative code generator configuration
ra_fixups :: [(BlockId, BlockId, BlockId)](from,fixup,to) : We inserted fixup code between from and to